SoC Designer Asynchronous AHB To AHB Bridge Cycle Approximat

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Figure 3-1: Connection of 2 AHB subsystems through an AHB2AHBAync bridge
The two AHB subsystems can be running on different clock domains. The
AHB2AHBAsync bridge interface can be used to connect AHB buses, where the
originating bus 1 is running at a clock frequency which is a multiple of that of the target
bus 2 or vice-versa.
Please refer the AMBA design kit TRM for further information.
3.1.1 Fully Functional and Approximate Features
The following features of the AHB2AHBAsync bridge hardware are implemented in the
AHB2AHBAsync bridge model. However the exact behavior of the hardware
implementation is not accurately reproduced because some approximations and
optimizations that have been made for simulation performance:
• 32 or 64 bit data bus.