SoC Designer AHBCache Model

http://www.cadfamily.com/a/EDA_PCB/ARM/SoC-Designer-AHBCache-Model_3776.html

AHBCache is an AHB compliant generic cache model. The model supports the following
features. This component does not model any specific IP.
The features of the model are :
• Direct mapped and set associative operation with 2, 4, or 8-way set associativity.
• Write back and write through modes.
• Allocate on read and write miss, and write around for write through mode only.
• User selectable critical word first read operation
• AHB compatible slave port for the CPU.
• AHB compatible master port for peripherals and system memory.
• Minimum cache size of 1 KB and a default memory size of 128 KB.
• Configurable access to the memory with width of 32/64 bits.
• Configurable cache line size width with default value of 32 bytes.
• Support for 4 non cacheable areas in the memory.
• Support for using HPROT control bit for cache access.
• Cache replacement using a random replacement policy.
• Model only supports little endianness at this point.