Codevision AT90SC Complete datasheet available under NDA

http://www.cadfamily.com/downinfo/302488.html

8-bit RISC Microcontroller CPU: AVR
The AVR uses a Harvard architecture concept with sepa-
rate memories and buses for program and data. The pro-
gram memory is accessed with a two stage pipeline. While
one instruction is being executed, the next instruction is
prefetched from the program memory. This concept
enables instructions to be executed in every clock cycle.
The fast-access register file concept contains 32 x 8 gen-
eral purpose working registers with a single clock cycle
access time. This means that during one single clock cycle,
one ALU operation is executed. Two operands are output
from the register file, the operation is executed, and the
result is stored back in the register file in one clock cycle.
The Timer and other I/O functions are located in the I/O
memory space. The 64 addresses of the I/O memory space
can be accessed directly as I/O registers or as memory
space.