Agilent Using Verilog-A and Verilog-AMS in Advanced Design System

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One powerful feature of Verilog-A is that a user can make modifications to the equationsthat describe the behavior of the device. These changes can be available in the simulatorautomatically, with no loss of analysis functionality. Many models will be distributed withtheir source code with the expectation that end-users will modify the equations for anynumber of reasons.

For example, the user may want the equations to better reflect someaspect of their device behavior, or they may want to delete code that is not necessary todescribe their device behavior, thereby improving simulation performance.In this example, the PSFETV model will be modified slightly. During simulation, theprogram searches for the source code based on pre-defined search paths (discussed indetail later), in the project directory veriloga, or as specifically defined using a VerilogA_Load component.1.If necessary, copy the project Tutorial_prj from the Examples/Verilog-A directory to a local directory. This tutorial contains a directory called veriloga that includes a filecalled psfetv.va .

This file is a copy of the parker_skellern.va file distributed in theVerilog-A Design Kit, with the module name changed to psfetv to prevent unintendedoverwriting of the other model.2.Open the design file tutorial_PSFETV.dsn and run a simulation to verify that the results are the same as the previous example.3.Using any text editor, open the psfetv.va file.