http://www.cadfamily.com/a/EDA_PCB/ARM/AHBICM-Model-Reference-Manual_3777.html
This section provides a summary of the functionality of the model. Note that the
AHBICM model does not model an existing ARM IP, and therefore no comparisons
(functional nor accuracy) against existing hardware are mentioned in this section.
2.1 Functionality
AHBICM is an add-on component to the AMBA AHB slave device. AHBICM connects up
to 8 AHB layers to a single shared slave in order to allow the slave to be used in a multilayer AHB system where multiple AHB layers require access to the same slave. Multilayer AHB designs offer higher bandwidth since multiple layers can access different
slave devices in parallel.
5/12/2015
SoC Designer Asynchronous AHB To AHB Bridge Cycle Approximat
http://www.cadfamily.com/a/EDA_PCB/ARM/SoC-Designer-Asynchronous-AHB-To-AHB-Bridge-Cycle-Approximat_3774.html
Figure 3-1: Connection of 2 AHB subsystems through an AHB2AHBAync bridge
The two AHB subsystems can be running on different clock domains. The
AHB2AHBAsync bridge interface can be used to connect AHB buses, where the
originating bus 1 is running at a clock frequency which is a multiple of that of the target
bus 2 or vice-versa.
Please refer the AMBA design kit TRM for further information.
3.1.1 Fully Functional and Approximate Features
The following features of the AHB2AHBAsync bridge hardware are implemented in the
AHB2AHBAsync bridge model. However the exact behavior of the hardware
implementation is not accurately reproduced because some approximations and
optimizations that have been made for simulation performance:
• 32 or 64 bit data bus.
Figure 3-1: Connection of 2 AHB subsystems through an AHB2AHBAync bridge
The two AHB subsystems can be running on different clock domains. The
AHB2AHBAsync bridge interface can be used to connect AHB buses, where the
originating bus 1 is running at a clock frequency which is a multiple of that of the target
bus 2 or vice-versa.
Please refer the AMBA design kit TRM for further information.
3.1.1 Fully Functional and Approximate Features
The following features of the AHB2AHBAsync bridge hardware are implemented in the
AHB2AHBAsync bridge model. However the exact behavior of the hardware
implementation is not accurately reproduced because some approximations and
optimizations that have been made for simulation performance:
• 32 or 64 bit data bus.
SoC Designer AHB2Mx Cycle Accurate Model
http://www.cadfamily.com/a/EDA_PCB/ARM/SoC-Designer-AHB2Mx-Cycle-Accurate-Model_3775.html
2.2 Performance
The performance on the AHB2Mx CA model has been measured using the following
example system provided with the AHB2Mx in the AMBA2 package.
CPU : Intel(R) Xeon™ CPU 3.40GHz
RAM : 2GB
OS : RedHat Enterprise 3.0
Bogomips : 6789.52
The speed of the system was measured by running the AHB stub based system given in
the examples. The system uses an AHB2Mx bridge. The system used, is same as the
one shown in Figure-7-1. The performance on the example system is 45,100 cyclesc.
2.2 Performance
The performance on the AHB2Mx CA model has been measured using the following
example system provided with the AHB2Mx in the AMBA2 package.
CPU : Intel(R) Xeon™ CPU 3.40GHz
RAM : 2GB
OS : RedHat Enterprise 3.0
Bogomips : 6789.52
The speed of the system was measured by running the AHB stub based system given in
the examples. The system uses an AHB2Mx bridge. The system used, is same as the
one shown in Figure-7-1. The performance on the example system is 45,100 cyclesc.
WRITING DEVICE HEADER FILES
http://www.cadfamily.com/a/EDA_PCB/ARM/WRITING-DEVICE-HEADER-FILES_3773.html
Useful documents
There are some useful documents to help you write header files.
•IAR code standards (CppGuide.html)
•IAR header file template (EWARM_HeaderTemplate.doc)
Where to start
A few pointers:
1. Find the relevant and up-to-date device user guide (can usually be downloaded from the chip manufacturer’s web
site).
2. Check if IAR Systems already supports more devices from the same family. You can often re-use parts from other
header files belonging to the same chip family.
What is included in a header file?
A header file can be said to consist of 6 sections:
1. A header with the following information:
• Which IAR Compiler and Assembler that the header file designed for
• that the header file is used with ARM IAR C/C++ Compiler and Assembler
• IAR Systems copyright information and the header file creation year
• File revision: $ Revision $
2. Protection against multiple inclusions of the same header file
Useful documents
There are some useful documents to help you write header files.
•IAR code standards (CppGuide.html)
•IAR header file template (EWARM_HeaderTemplate.doc)
Where to start
A few pointers:
1. Find the relevant and up-to-date device user guide (can usually be downloaded from the chip manufacturer’s web
site).
2. Check if IAR Systems already supports more devices from the same family. You can often re-use parts from other
header files belonging to the same chip family.
What is included in a header file?
A header file can be said to consist of 6 sections:
1. A header with the following information:
• Which IAR Compiler and Assembler that the header file designed for
• that the header file is used with ARM IAR C/C++ Compiler and Assembler
• IAR Systems copyright information and the header file creation year
• File revision: $ Revision $
2. Protection against multiple inclusions of the same header file
SoC Designer AHBCache Model
http://www.cadfamily.com/a/EDA_PCB/ARM/SoC-Designer-AHBCache-Model_3776.html
AHBCache is an AHB compliant generic cache model. The model supports the following
features. This component does not model any specific IP.
The features of the model are :
• Direct mapped and set associative operation with 2, 4, or 8-way set associativity.
• Write back and write through modes.
• Allocate on read and write miss, and write around for write through mode only.
• User selectable critical word first read operation
• AHB compatible slave port for the CPU.
• AHB compatible master port for peripherals and system memory.
• Minimum cache size of 1 KB and a default memory size of 128 KB.
• Configurable access to the memory with width of 32/64 bits.
• Configurable cache line size width with default value of 32 bytes.
• Support for 4 non cacheable areas in the memory.
• Support for using HPROT control bit for cache access.
• Cache replacement using a random replacement policy.
• Model only supports little endianness at this point.
AHBCache is an AHB compliant generic cache model. The model supports the following
features. This component does not model any specific IP.
The features of the model are :
• Direct mapped and set associative operation with 2, 4, or 8-way set associativity.
• Write back and write through modes.
• Allocate on read and write miss, and write around for write through mode only.
• User selectable critical word first read operation
• AHB compatible slave port for the CPU.
• AHB compatible master port for peripherals and system memory.
• Minimum cache size of 1 KB and a default memory size of 128 KB.
• Configurable access to the memory with width of 32/64 bits.
• Configurable cache line size width with default value of 32 bytes.
• Support for 4 non cacheable areas in the memory.
• Support for using HPROT control bit for cache access.
• Cache replacement using a random replacement policy.
• Model only supports little endianness at this point.
ARM ® Developer Suite Assembler Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/ARM--Developer-Suite-Assembler-Guide_3793.html
1.1 About the ARM Developer Suite assemblers
ARM Developer Suite (ADS) has:
• a freestanding assembler, armasm
• an optimizing inline assembler built into the C and C++ compilers.
The language that these assemblers take as input is basically the same. However, there
are limitations on what features of the language you can use in the inline assemblers.
Refer to the Mixing C, C++, and Assembly Language chapter in ADS Developer Guide
for further information on the inline assemblers.
The remainder of this book relates mainly to armasm
This chapter provides an introduction to the general principles of writing ARM and
Thumb assembly language. It contains the following sections:
1.1 About the ARM Developer Suite assemblers
ARM Developer Suite (ADS) has:
• a freestanding assembler, armasm
• an optimizing inline assembler built into the C and C++ compilers.
The language that these assemblers take as input is basically the same. However, there
are limitations on what features of the language you can use in the inline assemblers.
Refer to the Mixing C, C++, and Assembly Language chapter in ADS Developer Guide
for further information on the inline assemblers.
The remainder of this book relates mainly to armasm
This chapter provides an introduction to the general principles of writing ARM and
Thumb assembly language. It contains the following sections:
AS950 ARM Applications Library Programmer’s Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/AS950-ARM-Applications-Library-Programmer-s-Guide_3792.html
This book is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an introduction to the ARM Applications Library.
Chapter 2 Adaptive Differential Pulse Code Modulation
Read this chapter for details on implementation, and for function
descriptions for adaptive differential pulse code modulation (ADPCM).
Chapter 3 G.711 A-law, µ-law, PCM Conversions
Read this chapter for details on implementation, and for function
descriptions for the G.711 standard for A-law and µ-law conversion of
pulse code modulation (PCM) signals.
Chapter 4 Fast Fourier Transform and Windowing
Read this chapter for details on implementation, and for function
descriptions for the fast Fourier transform (FFT), and implementations of
Hamming and Hanning windows that can be used with the FFT.
Chapter 5 Two-Dimensional Discrete Cosine Transform
Read this chapter for details on implementation, and for function and
macro descriptions for two-dimensional (2D) discrete cosine transform
(DCT).
This book is organized into the following chapters:
Chapter 1 Introduction
Read this chapter for an introduction to the ARM Applications Library.
Chapter 2 Adaptive Differential Pulse Code Modulation
Read this chapter for details on implementation, and for function
descriptions for adaptive differential pulse code modulation (ADPCM).
Chapter 3 G.711 A-law, µ-law, PCM Conversions
Read this chapter for details on implementation, and for function
descriptions for the G.711 standard for A-law and µ-law conversion of
pulse code modulation (PCM) signals.
Chapter 4 Fast Fourier Transform and Windowing
Read this chapter for details on implementation, and for function
descriptions for the fast Fourier transform (FFT), and implementations of
Hamming and Hanning windows that can be used with the FFT.
Chapter 5 Two-Dimensional Discrete Cosine Transform
Read this chapter for details on implementation, and for function and
macro descriptions for two-dimensional (2D) discrete cosine transform
(DCT).
ARM ® Developer Suite AXD and armsd Debuggers Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/ARM--Developer-Suite-AXD-and-armsd-Debuggers-Guide_3794.html
1.1 Debugger concepts
This section introduces some of the concepts involved in debugging program images.
1.1.1 Debugger
A debugger is software that enables you to make use of a debug agent in order to
examine and control the execution of software running on a debug target. This part of
the book covers AXD, the ARM eXtended Debugger. The second part of this book
covers armsd, the ARM Symbolic Debugger.
1.1.2 Debug target
At an early stage of product development there might be no hardware. The expected
behavior of the product is simulated by software. Even though you might run this
software on the same computer as the debugger, it is useful to think of the target as a
separate piece of hardware.
1.1 Debugger concepts
This section introduces some of the concepts involved in debugging program images.
1.1.1 Debugger
A debugger is software that enables you to make use of a debug agent in order to
examine and control the execution of software running on a debug target. This part of
the book covers AXD, the ARM eXtended Debugger. The second part of this book
covers armsd, the ARM Symbolic Debugger.
1.1.2 Debug target
At an early stage of product development there might be no hardware. The expected
behavior of the product is simulated by software. Even though you might run this
software on the same computer as the debugger, it is useful to think of the target as a
separate piece of hardware.
ARM ® Developer Suite CodeWarrior® IDE Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/ARM--Developer-Suite-CodeWarrior-IDE-Guide_3795.html
• See Chapter 9 Configuring a Build Target for information on configuring the
ARM toolchain from within the CodeWarrior IDE.
1.3.1 Online documentation and online help
Documentation for the CodeWarrior IDE for the ARM Developer Suite is available
online as part of the ARM Developer Suite documentation collection. If you have
installed ADS using the default name, select Programs → ARM Developer Suite
v1.2 → Online Books from the Windows Start menu to access the collection.
In addition, the CodeWarrior IDE for the ARM Developer Suite provides
context-sensitive online help. You can access this in either of the following ways:
• Click on the question mark icon at the top right corner of the window. A question
mark appears alongside the mouse pointer. Click with the mouse pointer on the
item that you want help with.
• See Chapter 9 Configuring a Build Target for information on configuring the
ARM toolchain from within the CodeWarrior IDE.
1.3.1 Online documentation and online help
Documentation for the CodeWarrior IDE for the ARM Developer Suite is available
online as part of the ARM Developer Suite documentation collection. If you have
installed ADS using the default name, select Programs → ARM Developer Suite
v1.2 → Online Books from the Windows Start menu to access the collection.
In addition, the CodeWarrior IDE for the ARM Developer Suite provides
context-sensitive online help. You can access this in either of the following ways:
• Click on the question mark icon at the top right corner of the window. A question
mark appears alongside the mouse pointer. Click with the mouse pointer on the
item that you want help with.
PowerPac -- Getting Started with IAR Embedded Workbench®
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----Getting-Started-with-IAR-Embedded-Workbench_9975.html
Programming languages
There are two high-level programming languages you can use with the IAR
C/C++ Compiler:
● C, which follows the standard ISO 9899:1990 (commonly known as
ANSI C).
● C++ (depends on your product package). IAR Systems supports two
levels of the C++ language:
● Embedded C++ (EC++), a subset of the C++ programming standard. It
is defined by an industry consortium, the Embedded C++ Technical
committee.
● IAR Extended Embedded C++, with additional features such as full
template support, multiple inheritance (depending on your product
package), namespace support, the new cast operators, as well as the
Standard Template Library (STL).
PowerPac -- 8051 IAR C/C++ Compiler Reference Guide for the
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----8051-IAR-C-C---Compiler-Reference-Guide-for-the_9973.html
RUNTIME ENVIRONMENT
To create the required runtime environment you should choose a runtime library and set
library options. You may also need to override certain library modules with your own
customized versions.
There are two different sets of runtime libraries provided:
● The IAR DLIB Library, which supports ISO/ANSI C and C++. This library also
supports floating-point numbers in IEEE 754 format and it can be configured to
include different levels of support for locale, file descriptors, multibyte characters,
et cetera. (This library is the default for the C++ language).
● The IAR CLIB Library is a light-weight library, which is not fully compliant with
ISO/ANSI C. Neither does it fully support floating-point numbers in IEEE 754
format nor does it support Embedded C++. (This library is used by default for the C
language).
PowerPac -- ARM® IAR Embedded Workbench マイグレーション
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----ARM-IAR-Embedded-Workbench---------_9979.html
XLINKと ILINK
XLINKと ILINKは両方とも、 1つ以上の再配置可能オブジェクトファイルと 1
つ以上のオブジェクトライブラリの指定部分を結合し、実行可能イメージを
生成します。 XLINKでは、 IARシステムズのツールによって生成される
UBROFフォーマットのオブジェクトファイルしか入力に使用できません。出
力は、 UBROFまたは XLINKがサポートしているその他の出力フォーマットで
行われます。 ILINKでは、 ELFフォーマットのオブジェクトファイルを入力に
使用し、 ELFフォーマットの実行可能イメージを生成します。
バージョン 4.xでは、コンパイラはコードおよびデータを UBROFのセグメント
に配置します。このセグメントは、 XLINKにより、リンカコマンドファイル
で指定されているディレクティブに従って、メモリに配置されます。リンカ
コマンドファイルは、コマンドラインを拡張したもので、あらゆる XLINKの
コマンドラインオプションを指定するこ とができます。バージョン 5.xでは、
コンパイラはコードおよびデータを ELFのセクションに配置します。
PowerPac -- IAR C/C++ Development Guide Compiling and linkin
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----IAR-C-C---Development-Guide-Compiling-and-linkin_9977.html
The DLIB runtime
environment
This chapter describes the runtime environment in which an application
executes. In particular, the chapter covers the DLIB runtime library and how
you can modify it—setting options, overriding default library modules, or
building your own library—to optimize it for your application.
The chapter also covers system initialization and termination; how an
application can control what happens before the function main is called, and
how you can customize the initialization.
The chapter then describes how to configure functionality like locale and file
I/O, how to get C-SPY® runtime support, and how to prevent incompatible
modules from being linked together.
PowerPac -- IAR C/C++ 開発ガイド コンパイルおよびリ
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----IAR-C-C------------------_9978.html
注 : 別のベンダのコンパイラで生成されたモジュールをリンクするには、そ
のベンダの追加サポートライブラリが必要になることがあります。
IAR ILINK リンカでは、オブジェクトファイルに含まれる属性に基づき、使
用する適切な標準 C/C++ ライブラリが自動的に選択されます。 インポートさ
れるオブジェクトファイルには、これらのすべての属性が含まれないことが
あります。 そのため、このような場合、以下の 1 つ以上の項目を検証して、
ILINK による標準ライブラリの選択をサポートする必要があります。
● 使用する CPU (--cpu リンカオプションを指定 )。
● フル I/O が必要な場合、 フルライブラリ設定の標準ライブラリとリンクする
必要がある。
● --no_library_search リンカオプションとの組み合わせが可能な、ランタ
イムライブラリファイルを明示的に指定する。
PowerPac -- AVR® IAR embedded Workbench® IDE Migration
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----AVR-IAR-em-x-bedded-Workbench-IDE-Migration-G_9983.html
Project file and project setup
The workspace and projects you have created with EWA90 are not compatibe with
EWAVR. If you are using the IAR Embedded Workbench IDE, follow these steps to
convert your project file manually:
1 Start your new version of the AVR IAR Embedded Workbench IDE and create a new
workspace by choosing File>New and then Workspace.
2 Choose Project>Create New Project to create a new project. To add your source code
files, choose Project>Add files. For detailed information about how to create
workspace and projects, see the tutorials available in the AVR IAR Embedded
Workbench User Guide.
PowerPac -- AVR® IAR C/C++ Compiler Reference Guide for Atme
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----AVR-IAR-C-C---Compiler-Reference-Guide-for-Atme_9982.html
This section contains examples and descriptions of the segments used for storing code,
in other words, functions, and the interrupt vector table. Typically, these segments are
placed in the code memory space (flash).
The -Z command is used for defining all segments in the following examples. The
addresses used in the examples are based on the assumed target system described in the
Table 10, Memory layout of a target system (example), on page 35. Note that because
the described target system is limited in size of code memory space, several segments
supported by the compiler are not applicable for this target system.
For a complete list of all segments, see Summary of segments, page 149.
PowerPac -- QuickStart Card Upgrading an IAR Powerpac Produc
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----QuickStart-Card-Upgrading-an-IAR-Powerpac-Produc_9985.html
Upgrading the license server
Product upgrades for network licenses might come with an
upgrade CD for the license server software. If that is the case,
perform the following steps on the same computer where you
have the current license server software installed.
Note: This will shut down the license server and make all
network licenses temporarily unavailable.
1 First uninstall the current version of the license server
software by selecting the appropriate Uninstall IAR
License Server item from the Start menu.
2 Insert the installation CD. The installation program
should start automatically. If it does not, run the
a u t o r u n . e x e program from the CD.
PowerPac -- QuickStart Card Installing IAR PowerPac™ using
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----QuickStart-Card-Installing-IAR-PowerPac-using_9987.html
The installation procedure
The installation of IAR PowerPac™ is a three-stage
procedure:
A First you install the IAR Systems software using a
QuickStart key, which allows you to use the product
for 30 days.
B During this 30-day period, you must activate your
license by registering the product with IAR Systems.
Within 5 business days, you will receive a permanent
key for your license.
C Finally you install the permanent key. This opens up the
product for permanent usage.
Follow the detailed steps below for each stage.
A. Installing the software
1 Remove any dongles.
2 Insert the installation CD. The installation program
should start automatically. If it does not, run the
autorun.exe program from the CD.
PowerPac -- QuickStart Card Installing IAR embedded Workb
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----QuickStart-Card-Installing-IAR-em-x-bedded-Workb_9988.html
The installation procedure
The IAR Embedded Workbench® installation is a three-stage
procedure:
A First you install the IAR Systems software using a
QuickStart key, which allows you to use the product
for 30 days.
B During this 30-day period, you must activate your
license by registering the product with IAR Systems.
Within 5 business days, you will receive a permanent
key for your license.
C Finally you install the permanent key. This opens up the
product for permanent usage.
Follow the detailed steps below for each stage.
A. Installing the software
1 Remove any dongles.
2 Insert the IAR Embedded Workbench installation CD.
The installation program should start automatically. If it
does not, run the autorun.exe program from the CD.
3 Select Install IAR Embedded Workbench®.
4 You must accept the license agreement when prompted.
By clicking the Accept button, you confirm that you
have read and understood the license agreement.
PowerPac -- QuickStart Card
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----QuickStart-Card_9989.html
Installing IAR PowerPac™ for MSP430
The installation of IAR PowerPac for MSP430 requires that a compatible version of IAR
Embedded Workbench for MSP430 is installed on the PC. Check the file readme.htm
on the installation CD for information about compatible versions of IAR Embedded
Workbench for MSP430.
Step by step installation
1. Shut down IAR Embedded Workbench for MSP430.
2. Insert the IAR PowerPac for MSP430 installation CD. The installation program
should start automatically. If it does not, start autorun.exe from the CD.
3. Select Install IAR PowerPac™ for MSP430.
4. You must accept the license agreement when prompted. By selecting I accept the
terms of the license agreement, you confirm that you have read and understood
the license agreement.
PowerPac -- IAR PowerPac™ USB User Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----IAR-PowerPac-USB-User-Guide_9992.html
START WITHOUT USING AN EXAMPLE PROJECT
The best and easiest way to get started is to take a look at the IAR PowerPac USB example projects. IAR PowerPac
USB provides USB device drivers for some USB controllers. Using one of these drivers makes it easy to get the target
up and running. Refer to section Available USB drivers on page 93 for a list of all supported devices and their valid
identifiers.
If you are going to use IAR PowerPac USB with your own hardware, you might have to write your own device driver.
A driver template for the implementation is supplied. The template is located in
the<$TOOLCHAIN_DIR$>\PowerPac\USB\Example\Driver\ directory. If you do not want to start with one of the
supplied example projects, you have to perform the following steps to get the target system to behave like a mass storage
device or generic bulk device on the USB bus:
PowerPac -- IAR PowerPac™ TCP/IP Stack User Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----IAR-PowerPac-TCP-IP-Stack-User-Guide_9993.html
ADDING THE TCP/IP STACK TO AN EXISTING PROJECT
If you want to use the TCP/IP stack in an existing project, you have to add the IAR PowerPac TCP/IP library consistent
to your project requirements.
1 Select Project | Add files and select Library/Object Files (*.r*, *.a, *.o) in the Files of type list. The default
location of the prebuilt IAR PowerPac TCP/IP libraries is Powerpac\TCPIP\Lib. Choose the library of your choice
and confirm it with the Open button.
2 Add the compatible configuration file to your project (for example, IP_Config_SAM7X.c). The configuration file is
located in the corresponding driver subdirectory of the TCPIP\Example\Config directory.
3 You have to add the include path to your project settings. The include path is the path in which the compiler looks for
include files. In cases where the included files (typically header files, .h) do not reside in the same directory as the C
file to compile, an include path needs to be set. To build the project with the added library, choose Project | Options |
C/C++ Compiler | Preprocessor and add the following path to the Additional include directories field:
PowerPac -- IAR PowerPac™ RTOS for ARM Cores
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----IAR-PowerPac-RTOS-for-ARM-Cores_9994.html
Required files for an IAR PowerPac RTOS application
To build an application using IAR PowerPac RTOS, the following files from your IAR PowerPac RTOS distribution
are required and have to be included in your project:
● RTOS.h available in the subfolder RTOS\Inc\.
This header file declares all IAR PowerPac RTOS API functions and data types and has to be included in any
source file that uses IAR PowerPac RTOS functions.
● RTOSInit_*.c available in the BoardSupport\[Manufacturer]\[CPU]\Setup subfolder.
It contains hardware-dependent initialization code for IAR PowerPac RTOS timer.
● One IAR PowerPac RTOS library available in the subfolder RTOS\Lib\.
IAR PowerPac™ RTOS User Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/IAR-PowerPac-RTOS-User-Guide_9996.html
PRIORITY-CONTROLLED SCHEDULING ALGORITHM
In real-world applications, different tasks require different response times. For example, in an application that controls
a motor, a keyboard, and a display, the motor usually requires faster reaction time than the keyboard and display. While
the display is being updated, the motor needs to be controlled. This makes preemptive multitasking a must. Roundrobin might work, but because it cannot guarantee a specific reaction time, an improved algorithm should be used.
In priority-controlled scheduling, every task is assigned a priority. The order of execution depends on this priority. The
rule is very simple:
PowerPac -- IAR PowerPac™ GUI User Guide Graphic library
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----IAR-PowerPac-GUI-User-Guide-Graphic-library-wi_9997.html
Using the simulator
The IAR PowerPac GUI simulator requires Microsoft Visual C++ (version 6.00 or higher) and the integrated
development environment (IDE) which comes with it. You will see a simulation of your LCD on your PC screen, which
has the same resolution in X and Y and can display the exact same colors as your LCD once it has been properly
configured. The entire graphic library API and window manager API of the simulation are identical to those on your
target system; all functions will behave in the very same way as on the target hardware since the simulation uses the
same C source code as the target system. The difference lies only in the lower level of the software: the LCD driver.
Instead of using the actual LCD driver, the PC simulation uses a simulation driver which writes into a bitmap. The
bitmap is then displayed on your screen using a second thread of the simulation. This second thread is invisible to the
application; it behaves just as if the LCD routines were writing directly to the display.
PowerPac -- ORTI Plug-in for the IAR Embedded Workbench C-SP
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----ORTI-Plug-in-for-the-IAR-Embedded-Workbench-C-SP_10000.html
General Inspection Windows
The other windows shown on the ORTI view menu are inspection windows of different kind. The number
and type of windows depend on the information in the ORTI input file.
Inspection window context menu
The context menu available in an inspection
window provides commands to:
• Automatically resize column widths.
• Toggle gridlines on or off. On is marked with a
check mark.
Note: When gridlines are shown and column
widths are resized the window contents
may flicker during redraw
• Numeric value display, binary octal, decimal, or
hexadecimal. The current display type is marked
with a check mark.
• View properties of the item pointed to by the
cursor.
IAR PowerPac™ File System User Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/IAR-PowerPac-File-System-User-Guide_9999.html
ADJUSTING THE RAM USAGE
The file system needs RAM for management purposes in various places. The amount of RAM required depends
primarily on the configuration, especially on the drivers used. The drivers which have their own level of management
(such as NOR / NAND drivers) in general need more RAM than the "simple" drivers for hard drives, CompactFlash or
SD cards.
Every driver needs to allocate RAM. The file system allocates RAM in the initialization phase and holds it while the
file system is running. The macro ALLOC_SIZE which is located in the respective driver configuration file specifies the
size of RAM used by the file system. This value should be fine-tuned according to the requirements of your target
system.
PowerPac -- IAR PowerPac™ File System User Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/PowerPac----IAR-PowerPac-File-System-User-Guide_9998.html
ADJUSTING THE RAM USAGE
The file system needs RAM for management purposes in various places. The amount of RAM required depends
primarily on the configuration, especially on the drivers used. The drivers which have their own level of management
(such as NOR / NAND drivers) in general need more RAM than the "simple" drivers for hard drives, compact flash or
SD cards.
Every driver needs to allocate RAM. The file system allocates RAM in the initialization phase and holds it while the
file system is running. The macro ALLOC_SIZE which is located in the respective driver configuration file specifies the
size of RAM used by the file system. This value should be fine-tuned according to the requirements of your target
system.
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