http://www.cadfamily.com/a/EDA_PCB/ARM/AHBICM-Model-Reference-Manual_3777.html
This section provides a summary of the functionality of the model. Note that the
AHBICM model does not model an existing ARM IP, and therefore no comparisons
(functional nor accuracy) against existing hardware are mentioned in this section.
2.1 Functionality
AHBICM is an add-on component to the AMBA AHB slave device. AHBICM connects up
to 8 AHB layers to a single shared slave in order to allow the slave to be used in a multilayer AHB system where multiple AHB layers require access to the same slave. Multilayer AHB designs offer higher bandwidth since multiple layers can access different
slave devices in parallel.
5/12/2015
SoC Designer Asynchronous AHB To AHB Bridge Cycle Approximat
http://www.cadfamily.com/a/EDA_PCB/ARM/SoC-Designer-Asynchronous-AHB-To-AHB-Bridge-Cycle-Approximat_3774.html
Figure 3-1: Connection of 2 AHB subsystems through an AHB2AHBAync bridge
The two AHB subsystems can be running on different clock domains. The
AHB2AHBAsync bridge interface can be used to connect AHB buses, where the
originating bus 1 is running at a clock frequency which is a multiple of that of the target
bus 2 or vice-versa.
Please refer the AMBA design kit TRM for further information.
3.1.1 Fully Functional and Approximate Features
The following features of the AHB2AHBAsync bridge hardware are implemented in the
AHB2AHBAsync bridge model. However the exact behavior of the hardware
implementation is not accurately reproduced because some approximations and
optimizations that have been made for simulation performance:
• 32 or 64 bit data bus.
Figure 3-1: Connection of 2 AHB subsystems through an AHB2AHBAync bridge
The two AHB subsystems can be running on different clock domains. The
AHB2AHBAsync bridge interface can be used to connect AHB buses, where the
originating bus 1 is running at a clock frequency which is a multiple of that of the target
bus 2 or vice-versa.
Please refer the AMBA design kit TRM for further information.
3.1.1 Fully Functional and Approximate Features
The following features of the AHB2AHBAsync bridge hardware are implemented in the
AHB2AHBAsync bridge model. However the exact behavior of the hardware
implementation is not accurately reproduced because some approximations and
optimizations that have been made for simulation performance:
• 32 or 64 bit data bus.
SoC Designer AHB2Mx Cycle Accurate Model
http://www.cadfamily.com/a/EDA_PCB/ARM/SoC-Designer-AHB2Mx-Cycle-Accurate-Model_3775.html
2.2 Performance
The performance on the AHB2Mx CA model has been measured using the following
example system provided with the AHB2Mx in the AMBA2 package.
CPU : Intel(R) Xeon™ CPU 3.40GHz
RAM : 2GB
OS : RedHat Enterprise 3.0
Bogomips : 6789.52
The speed of the system was measured by running the AHB stub based system given in
the examples. The system uses an AHB2Mx bridge. The system used, is same as the
one shown in Figure-7-1. The performance on the example system is 45,100 cyclesc.
2.2 Performance
The performance on the AHB2Mx CA model has been measured using the following
example system provided with the AHB2Mx in the AMBA2 package.
CPU : Intel(R) Xeon™ CPU 3.40GHz
RAM : 2GB
OS : RedHat Enterprise 3.0
Bogomips : 6789.52
The speed of the system was measured by running the AHB stub based system given in
the examples. The system uses an AHB2Mx bridge. The system used, is same as the
one shown in Figure-7-1. The performance on the example system is 45,100 cyclesc.
WRITING DEVICE HEADER FILES
http://www.cadfamily.com/a/EDA_PCB/ARM/WRITING-DEVICE-HEADER-FILES_3773.html
Useful documents
There are some useful documents to help you write header files.
•IAR code standards (CppGuide.html)
•IAR header file template (EWARM_HeaderTemplate.doc)
Where to start
A few pointers:
1. Find the relevant and up-to-date device user guide (can usually be downloaded from the chip manufacturer’s web
site).
2. Check if IAR Systems already supports more devices from the same family. You can often re-use parts from other
header files belonging to the same chip family.
What is included in a header file?
A header file can be said to consist of 6 sections:
1. A header with the following information:
• Which IAR Compiler and Assembler that the header file designed for
• that the header file is used with ARM IAR C/C++ Compiler and Assembler
• IAR Systems copyright information and the header file creation year
• File revision: $ Revision $
2. Protection against multiple inclusions of the same header file
Useful documents
There are some useful documents to help you write header files.
•IAR code standards (CppGuide.html)
•IAR header file template (EWARM_HeaderTemplate.doc)
Where to start
A few pointers:
1. Find the relevant and up-to-date device user guide (can usually be downloaded from the chip manufacturer’s web
site).
2. Check if IAR Systems already supports more devices from the same family. You can often re-use parts from other
header files belonging to the same chip family.
What is included in a header file?
A header file can be said to consist of 6 sections:
1. A header with the following information:
• Which IAR Compiler and Assembler that the header file designed for
• that the header file is used with ARM IAR C/C++ Compiler and Assembler
• IAR Systems copyright information and the header file creation year
• File revision: $ Revision $
2. Protection against multiple inclusions of the same header file
SoC Designer AHBCache Model
http://www.cadfamily.com/a/EDA_PCB/ARM/SoC-Designer-AHBCache-Model_3776.html
AHBCache is an AHB compliant generic cache model. The model supports the following
features. This component does not model any specific IP.
The features of the model are :
• Direct mapped and set associative operation with 2, 4, or 8-way set associativity.
• Write back and write through modes.
• Allocate on read and write miss, and write around for write through mode only.
• User selectable critical word first read operation
• AHB compatible slave port for the CPU.
• AHB compatible master port for peripherals and system memory.
• Minimum cache size of 1 KB and a default memory size of 128 KB.
• Configurable access to the memory with width of 32/64 bits.
• Configurable cache line size width with default value of 32 bytes.
• Support for 4 non cacheable areas in the memory.
• Support for using HPROT control bit for cache access.
• Cache replacement using a random replacement policy.
• Model only supports little endianness at this point.
AHBCache is an AHB compliant generic cache model. The model supports the following
features. This component does not model any specific IP.
The features of the model are :
• Direct mapped and set associative operation with 2, 4, or 8-way set associativity.
• Write back and write through modes.
• Allocate on read and write miss, and write around for write through mode only.
• User selectable critical word first read operation
• AHB compatible slave port for the CPU.
• AHB compatible master port for peripherals and system memory.
• Minimum cache size of 1 KB and a default memory size of 128 KB.
• Configurable access to the memory with width of 32/64 bits.
• Configurable cache line size width with default value of 32 bytes.
• Support for 4 non cacheable areas in the memory.
• Support for using HPROT control bit for cache access.
• Cache replacement using a random replacement policy.
• Model only supports little endianness at this point.
ARM ® Developer Suite Assembler Guide
http://www.cadfamily.com/a/EDA_PCB/ARM/ARM--Developer-Suite-Assembler-Guide_3793.html
1.1 About the ARM Developer Suite assemblers
ARM Developer Suite (ADS) has:
• a freestanding assembler, armasm
• an optimizing inline assembler built into the C and C++ compilers.
The language that these assemblers take as input is basically the same. However, there
are limitations on what features of the language you can use in the inline assemblers.
Refer to the Mixing C, C++, and Assembly Language chapter in ADS Developer Guide
for further information on the inline assemblers.
The remainder of this book relates mainly to armasm
This chapter provides an introduction to the general principles of writing ARM and
Thumb assembly language. It contains the following sections:
1.1 About the ARM Developer Suite assemblers
ARM Developer Suite (ADS) has:
• a freestanding assembler, armasm
• an optimizing inline assembler built into the C and C++ compilers.
The language that these assemblers take as input is basically the same. However, there
are limitations on what features of the language you can use in the inline assemblers.
Refer to the Mixing C, C++, and Assembly Language chapter in ADS Developer Guide
for further information on the inline assemblers.
The remainder of this book relates mainly to armasm
This chapter provides an introduction to the general principles of writing ARM and
Thumb assembly language. It contains the following sections:
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